1. Technical Field
This invention relates to voltage regulators for integrated semiconductor circuits. More particularly, the invention relates to voltage regulators that supply load current during a load event where the load current during the load event is approximately known before the event occurs.
2. Description of Related Art
Dynamic random access memory (DRAM) chips commonly use large NMOS regulating transistors operated in the weak inversion mode to generate internal voltages. Some advantages of this type of voltage regulator are the wide external voltage operating range, the simplicity of design and the relatively low operating current.
In a typical design, a static bias voltage is generated by an oscillator/pump preregulator. The preregulator provides a relatively constant static bias voltage equal to the desired voltage regulator output voltage plus the threshold voltage of the NMOS regulating transistor. The static bias voltage is applied to the gate of the NMOS regulating transistor operating in the weak inversion mode. This generates the desired regulated output voltage at the source lead of the NMOS regulating transistor.
In order to generate a stable ripple free output, the static bias voltage must be held constant, and generally this is accomplished through the use of a relatively large gate capacitor located between the NMOS regulating transistor gate lead and ground.
One problem with this design is that the gate to source threshold voltage V.sub.t varies somewhat depending upon the current through the NMOS regulating transistor.
In a DRAM chip the load current varies from a relatively low standby current I.sub.STBY to a peak load current I.sub.PEAK which may be up to six orders of magnitude greater than the standby current. When prior art regulators are used in this application, the described fluctuation in threshold voltage as a function of load current appears as a fluctuation in the regulated output voltage. This fluctuation can cause problems with some circuits, particularly chip input receivers. Also, if the ratio between peak to average load current is high, for example in the set current of a DRAM array, worse voltage fluctuation results as the peak current I.sub.PEAK moves further into the NMOS overdrive region.
One approach to this problem would be to use feedback from the regulated voltage output of the voltage regulator to correct the input voltage at the gate of the regulating transistor. This would require a drive regulator circuit to detect that the output voltage was dropping as load current increased, which could then boost the voltage at the gate of the regulating transistor. However, in view of the high speed operation in modern DRAMs, this type of feedback would require a nearly perfect drive regulator feedback circuit providing nearly infinite gain and bandwidth. Otherwise, the boost in voltage at the gate of the regulating transistor would come too late to counteract the drop in voltage at the output.
In view of the absence of perfect feedback circuits of the type needed, this type of feedback method is not practical. However in certain applications, the current drawn by the load I.sub.LOAD is highly predictable. This is particularly true in the case of DRAM memory chips, where the shape of the load current curve is often known quite accurately. Typically the load current starts at a low standby current, then increases rapidly to a peak current value and then falls back to standby. This pulse of current during the load event occurs over a well defined time period.
For loads of this type, i.e. which have an approximately known load current characteristic shape during the load event, the boost voltage that would be produced by a fictitious perfect feedback circuit can be predicted in advance. This is possible by combining knowledge of the predicted load current with knowledge about the measured voltage drop characteristic of the NMOS regulating transistor as a function of load current.
Using this prediction, the necessary boost voltage from a perfect feedback circuit can be determined in advance. This allows an appropriate boost driver circuit to be built which is triggered by the same signal that starts the known load event. The boost driver circuit produces a shaped boost signal, which is then applied to the input of the regulating transistor and which completely or nearly completely counteracts the drop in output voltage that would otherwise have occurred.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a voltage regulator with reduced voltage fluctuation at its output during a short duration load event.
Yet another object of the invention is to provide a voltage regulator suitable for use in DRAM chips using large NMOS devices operating in the weak inversion mode to generate internal voltages with reduced voltage fluctuations.
A further object of the invention is to provide a voltage regulator for supplying load current during a load vent to a load having an approximately known load current characteristic during the load event wherein a boost driver circuit is used to simulate the output of an idealized perfect feedback circuit to boost the input voltage of the feedback transistor during the load event.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.